AD9508SCPZ-EP

AD9508-EP is a clock fan-out buffer with output dividers and delay. It provides clock fan-out capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications such as clocking data converters with demanding phase noise and low jitter requirements. It has four independent differential clock outputs, each with various types of logic levels available. Available logic types are LVDS (1.2GHz), HSTL (1.2GHz), and 1.8V CMOS (250MHz). In addition, this device supports coarse output phase adjustment between the outputs. The device can also be pin programmed for various fixed configurations at power-up without the need for SPI or I²C programming. It is used in application such as low jitter, low phase noise clock distribution, clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, high performance wireless transceivers, high performance instrumentation, broadband infrastructure etc.

• Pin strapping mode for hardwired programming at power-up
• Excellent output-to-output isolation
• Additive output jitter is 41fs rms typical (12KHz to 20MHz)
• Internal low dropout (LDO) voltage regulator for enhanced power supply immunity
• Automatic synchronization of all outputs
• Phase offset select for output-to-output coarse delay adjust
• Serial control port (SPI/I²C) or pin programmable mode
• 3 programmable output logic levels: LVDS, HSTL, and CMOS
• Operating temperature is -55°C to +105°C
• Package style is 24-lead lead frame chip scale [LFCSP]

Uwagi

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