DC1075B-A

DC1075B-A demonstration circuit is a divide by 4 clock divider for use with high speed ADCs. Each assembly includes a clock divider followed by a re-timing stage used to produce sharp clock edges. Functionally, the DC1075B receives a high frequency sine wave which is attenuated and routed into the clock divider. The output of the clock divider is then routed to a D flip flop re-timing stage. This D flip flop is clocked by the original high frequency sine wave. This is critical to ensure signal integrity. The output of this re-timing stage is a CMOS signal suitable to be a clock source for high speed ADCs. This circuit also is a model for designs involving FPGAs which serve as clock dividers. Whenever this is done, a D flip flop re-timing stage is required to ensure a low jitter clock signal.

• HMC433E low noise divide-by-4 Static Divider utilizing InGaP GaAs HBT technology
• 1100MHz maximum input frequency

Uwagi

Input frequencies for the DC1075B-A from 540MHz to 700MHz are not recommended.