TPS51100DGQR

The TPS51100DGQR is a 3A sink and source double-data-rate (DDR) Terminator Regulator. The device maintains fast transient response, only requiring 20µF (2 x 10µF) of ceramic output capacitance. The device supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The device also supports DDR3 VTT termination with VDDQ at 1.5V (typical). In addition, the device includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-OFF for VTT and VTTREF in S5 (suspend to disk).

• 3A Sink and source termination regulator Includes droop compensation
• 1.2V Input (VLDOIN) helps reduce total power dissipation
• Integrated divider tracks 0.5 VDDQSNS for VTT and VTTREF
• Remote sensing (VTTSNS)
• ±20mV Accuracy for VTT and VTTREF
• 10mA Buffered reference (VTTREF)
• Built-in soft-start, UVLO and OCL
• Thermal shutdown
• Supports JEDEC specifications
• Green product and no Sb/Br