AD6620ASZ

AD6620 digital receiver with four cascaded signal processing elements a frequency translator, two fixed coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compatible. As ADCs achieve higher sampling rates and dynamic range, it becomes increasingly attractive to accomplish the final IF stage of a receiver in the digital domain. Digital IF Processing is less expensive, easier to manufacture, more accurate, and more flexible than a comparable highly selective analogue stage. This diversity channel decimating receiver is designed to bridge the gap between high-speed ADCs and general purpose DSPs. The high resolution NCO allows a single carrier to be selected from a high speed data stream. High dynamic range decimation filters with a wide range of decimation rates allow both narrowband and wideband carriers to be extracted.

• High input sample rate, NCO frequency translation
• 2nd order cascaded integrator comb FIR filter linear phase, fixed coefficients
• 5th order cascaded integrator comb FIR filter linear phase, fixed coefficients
• Programmable decimating RAM coefficient FIR filter
• Bidirectional synchronization circuitry, phase aligns NCOs
• Synchronizes data output clocks, serial, parallel baseband outputs, pin selectable serial/parallel
• 16Bit parallel port, interleaved I and Q outputs, two separate control and configuration ports
• Generic µP port, serial port, JTAG boundary scan
• Typical logic compatibility is 3.3V CMOS
• 80-lead PQFP package, ambient temperature range from -40 to +85°C

Uwagi

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