AD9633BCPZ-125

AD9633BCPZ-125 is a quad, 12bit, 125MSPS analogue-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of upto 125MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signalling a new output byte are provided. It is used in applications such as medical ultrasound, high speed imaging, quadrature and diversity radio receivers, test equipment.

• Full chip and individual channel power-down modes, flexible bit orientation
• Built-in and custom digital test pattern generation, multichip sync and clock divider
• Programmable output clock and data alignment, programmable output resolution, standby mode
• Differential nonlinearity is +0.6LSB maximum at (AVDD = 1.8V, DRVDD = 1.8V)
• Signal to noise ratio is 71.8dBFS typical at (fIN = 9.7MHz, AVDD = 1.8V, DRVDD = 1.8V)
• Spurious-free dynamic range is 94dBc typical at (fIN = 9.7MHz, AVDD = 1.8V, DRVDD = 1.8V)
• Analog input bandwidth is 650MHz typical at (AVDD = 1.8V, DRVDD = 1.8V)
• Offset error is +0.1% FSR maximum at (AVDD = 1.8V, DRVDD = 1.8V)
• 2V p-p input voltage range, 1.8V supply operation
• Operating temperature range from -40°C to +85°C, 48-lead LFCSP package

Uwagi

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