AD9694TCPZ-500-EP

AD9694-EP is a quad analogue-to-digital converter. The device has an on-chip buffer and a sample and-hold circuit designed for low power, small size, and ease of use. This is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power. The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. It features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analogue inputs and clock signals are differential inputs. Each pair of ADC data outputs is internally connected to two digital downconverters (DDCs) through a crossbar mux. Application includes communications, diversity multiband, multimode digital receivers, 3G/4G, W-CDMA, GSM, LTE, LTE-A, general-purpose software radios, ultrawideband satellite receivers, instrumentation, radars, signals intelligence (SIGINT).

• JESD204B (Subclass 1) coded serial digital outputs
• 15Gbps maximum data rate per channel (nonreturn to zero (NRZ) (TA = 25°C))
• 415mW per ADC channel, 1.66W typical total power dissipation (TA = 25°C)
• 89dBFS typical spurious free dynamic range (AIN full scale = 1.44V p-p)
• 65.4dBFS typical signal to noise ratio (AIN full scale = 1.44V p-p)
• Typical noise density is -149.7dBFS/Hz (AIN full scale = 1.44V p-p)
• Power supply range from 0.95 to 1.00V (AVDD1, TA = 25°C)
• No missing codes, internal ADC voltage reference, analogue input buffer
• On-chip dithering to improve small signal linearity, differential clock input
• 72 Lead LFCSP package, ambient temperature range from -55°C to +105°C

Uwagi

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