CY2309SXI-1

CY2309SXI-1 is a low cost 3.3V zero delay buffer. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low skew clocks. This has on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The CY2309 PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25.0μA current draw for these parts. Multiple CY2309 device can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700ps.

• 16-pin SOIC (150 Mils) package type, industrial range
• 10MHz to 100/133MHz operating range, compatible with CPU and PCI bus frequencies
• Zero input-output propagation delay
• 60ps typical cycle-to-cycle jitter (high drive)
• Multiple low skew outputs, 85ps typical output-to-output skew
• One input drives nine outputs, grouped as 4 + 4 + 1
• Compatible with Pentium-based systems
• Test mode to bypass phase-locked loop (PLL)
• Ambient operating temperature range from 0 to 70°C