S912ZVCA19F0MLF

The S912ZVCA19F0MLF is a 16-bit Microcontroller based on S12Z CPU with CISC architecture operates at a maximum frequency of 32MHz. The device incorporates 192kB internal flash, 12kB internal RAM, 16-channel 12-bit A/D converter and 28 general-purpose I/O pins. The MC9S12ZVC-family is a new member of the S12 MagniV product line integrating a battery level (12V) voltage regulator, supply voltage monitoring, high voltage inputs and a CAN physical interface. It’s primarily targeting at CAN nodes like sensors, switch panels or small actuators. It offers various low-power modes and wakeup management to address state of the art power consumption requirements. The MC9S12ZVC-Family is based on the enhanced performance, linear address space S12Z core and delivers an optimized solution with the integration of several key system components into a single device, optimizing system architecture and achieving significant space savings.

• Harvard architecture - parallel data and code access
• 3-Stage pipeline
• 32-bit Wide instruction and data bus
• 32-bit ALU
• 24-bit Addressing (16MB linear address space)
• Background debug controller (BDC)
• Real time interrupt (RTI)
• Computer operating properly (COP) watchdog
• System reset generation
• Low power operation
• Internal phase-locked loop (IPLL)
• 1MHz Internal RC oscillator with +/-1.3% accuracy
• Amplitude controlled Pierce oscillator using 4MHz to 20MHz crystal (XOSCLCP)
• 8-channel Timer module (TIM0), 4-channel timer module (TIM1)
• 16-bit Pulse width modulation module (PWM0 and PWM1)
• Inter-IC module (IIC) - multimaster operation
• CAN physical layer (CANPHY)
• Multi-scalable controller area network (MSCAN)
• SENT transmitter (SENT_TX)
• Serial communication Interface module (SCI) - full duplex or single-wire operation
• Serial peripheral interface module (SPI) - full duplex or single-wire bidirectional
• 8-bit Resolution DAC
• Analog comparator module (ACMP)
• Supply voltage sensor (BATS)
• On-chip voltage regulator system (VREG)