ADF4377BCCZ

ADF4377 is a high performance, ultralow jitter, dual output integer-N phased locked loop (PLL) with an integrated voltage controlled oscillator (VCO) ideally suited for data converter and mixed signal front end (MxFE) clock applications. This integrates all necessary power supply bypass capacitors, saving board space on compact boards. For multiple data converter and MxFE clock applications, this simplifies clock alignment and calibration routines required with other clock solutions by implementing the automatic reference to output synchronization feature, the matched reference to output delays across process, voltage, and temperature feature, and the less than ±0.1 ps, jitter free reference to output delay adjustment capability feature. These features allow for predictable and precise multichip clock and system reference (SYSREF) alignment. Application includes high performance data converter and MxFE clocking, wireless infrastructure (MC-GSM, 5G), test and measurement.

• 800MHz to 12.8GHz output frequency range, 18fsrms typical RMS jitter (TA = -40 to +105°C)
• Typical phase noise floor is -160dBc/Hz (TA = -40°C to +105°C)
• 3 to 500MHz input frequency (TA = -40°C to +105°C)
• Reference input to output delay specifications
• 3ps device-to-device standard deviation
• 0.03ps/°C typical propagation delay temperature coefficient (REF-SEL = 0)
• <lt/>±0.1ps typical adjustment step size
• Multichip output phase alignment
• 1.75 to 1.9W typical power dissipation (ENCLK2 = low, V3.3V-1 = V3.3V-2 = 3.3V)
• 48 lead LGA package, temperature range from -40°C to +105°C

Uwagi

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