DS26503L+

The DS26503L+ is a T1/E1/J1 BITS element in 64 pin LQFP package. This is a building-integrated timing supply (BITS) clock-recovery element. It also functions as a basic T1/E1 transceiver. The receiver portion can recover a clock from T1, E1 and 6312KHz synchronization timing interfaces. In T1 and E1 modes, the synchronization status message (SSM) can also be recovered. The transmit portion can directly interface to T1 or E1 interfaces as well as source the SSM in T1 and E1 modes. The DS26503 can translate between any of the supported inbound synchronization clock rates to any supported outbound rate. A separate output is provided to source a 6312KHz clock. The device is controlled through a parallel, serial or hardware controller port. It is G.703 2048KHz synchronization interface and G.703 6312KHz Japanese synchronization interface compliant. It is used at BITS timing, rate conversion and basic transceiver.

• 3.3V (3.135 to 3.465V) supply with 5V-tolerant I/P and O/P, monitor mode for bridging applications
• Operating temperature range from 0°C to 70°C, IEEE 1149.1 JTAG boundary scan
• Accepts 16.384MHz, 12.8MHz, 8.192MHz, 4.096MHz, 2.048MHz or 1.544MHz master clock
• 8bit parallel control port, multiplexed or nonmultiplexed, Intel or Motorola
• Interfaces to standard T1/J1 (1.544MHz) and E1 (2.048MHz)
• Interface to CMI-coded T1/J1 and E1, short and long haul line interface
• Transmit and receive T1 and E1 SSM messages with message validation
• T1/E1 jitter attenuator with bypass mode, serial (SPI) control port, hardware control mode
• Fully independent transmit and receive functionality
• Internal software-selectable receive and transmit side termination for 75/100/110/120 ohm
• Basic Transceiver; BITS Timing; Rate Conversion

Uwagi

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