74HC4094PW,118

74HC4094PW,118 is an 8bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. This device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. It is used in applications such as serial-to-parallel data conversion, remote control holding register.

• Complies with JEDEC standard JESD7A
• CMOS input level, low-power dissipation
• ESD protection: HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V
• Supply voltage range from 2V to 6V
• Input leakage current is ±0.1μA maximum at (VI = VCC or GND; VCC = 6.0V, 25°C)
• OFF-state output current is ±0.5 maximum at (VI = VIH or VIL; VO = VCC or GND; VCC = 6V, 25°C)
• Supply current is 8μA maximum at (VI = VCC or GND; IO = 0A; VCC = 6V, 25°C)
• Input capacitance is 3.5pF typical at (25°C)
• Propagation delay is 50ns typical at (VCC = 2V, 25°C)
• Operating temperature range from -40°C to +125°C, TSSOP16 package

Ostrzeżenia

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.