STM8S207SBT6C

STM8S207SBT6C is a mainstream performance line 8bit MCU with 128Kbytes flash, 24MHz CPU, integrated EEPROM. It is referred to as high-density device in the STM8S MCU family reference manual. It provides reduced system cost, performance robustness, short development cycles, and product longevity. The system cost is reduced thanks to an integrated true data EEPROM for up to 300K write/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset. Device performance is ensured by 20 MIPS at 24MHz CPU clock frequency and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system. Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals. Full documentation is offered with a wide choice of development tools.

• Max fCPU: up to 24MHz, 0 wait states at fCPU≤ 16MHz and extended instruction set
• Advanced STM8 core with Harvard architecture and 3-stage pipeline
• Data up to 2Kbytes true data EEPROM, endurance 300k cycles and RAM up to 6Kbytes
• 2.95 to 5.5V operating voltage
• Low power crystal resonator oscillator, external clock input
• Clock security system with clock monitor, peripheral clocks switched off individually
• Wait, active-halt, & halt low power modes
• 8-bit basic timer with 8-bit prescaler, auto wakeup timer, Window watchdog, independent watchdog
• URAT, SPI, I2C interfaces
• Up to 68 I/Os on 80 pin package including 18 high sink O/Ps and 96-bit unique ID key for each device

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